Half wave voltage divider

ABSTRACT

An electrical circuit is provided in which a bank of capacitors is controllably charged in series and then discharged in parallel through the interaction of a voltage divider, a silicon controlled rectifier, and diode circuit elements to transform a sinusoidal line voltage into a half-wave pulse. The magnitude of the pulse is a function of the RMS line voltage input and the number of capacitors in the bank. This function may be expressed as 1/(k).V/n where V is the RMS line voltage input, n is the number of capacitors in the banks and k is the transformation and round-off error constant.

[111 3,743,914 i451 'July 3,1973

[ HALF WAVE VOLTAGE DIVIDER [75] inventor: George E. Holz, NorthPlainfield,

[73] Assignee: Burroughs Corporation, Detroit,

Mich.

[22] Filed: Jan. 17, 1972 [21] Appl. No.: 218,088

3,596,369 8/1971 Dickerson 320/1 X Primary Examiner-Bemard KonickAssistant Examiner stuart N. Hecker Attorney-Charles S. Hall 57 ABSTRACTAn electrical circuit is provided in which a bank of capacitors iscontrollably charged in series and then discharged in parallel throughthe interaction of a voltage divider, a silicon controlled rectifier,and diode circuit elements to transform a sinusoidal line voltage into ahalf-wave pulse. The magnitude of the pulse is a function of the RMSline voltage input and the number of capacitors in the bank. Thisfunction may be expressed as l/(k)-V/n where V is the RMS line voltageinput, 11 is the number of capacitors in the banks and k is thetransformation and round-off error constant.

7 Claims, 4 Drawing Figures Patented July 3, 1973 2 Sheets-Sheet 1 ourFig]

43 our 2H5 vii 4T /29 31 as f- 49 Patented July 3, 1973 2 Sheets-Sheet 2RN \RIT VIN MODE 0 0 MODE F o NUDE E o NODE H o HALF WAVE VOLTAGEDIVIDER BACKGROUND OF THE INVENTION bulky and require relatively highpower and generate sufficient heat to make them unsuitable for someapplications.

SUMMARY OF THE INVENTION An object of this invention, therefore, is todivide a sinusoidal voltage peak magnitude, efficiently and with aminimum of power loss, into a series of output pulses whose magnitude isa function of the divisional factor.

Capacitors of equal value are changed in series and discharged inparallel by applying a reference potential to a diode switching networkthrough a silicon controlled rectifier having its gate tied to the inputvoltage. The switching of the SCR between conducting and non-conductingstates allows the capacitors to charge during one half of the inputsinusoidal voltage cycle and to discharge during the other half cycle.The output pulse of this device is a decaying exponential of thefrequency of the input, which may be smoothed to a DC level by properoutput filtering, and whose magnitude is inversely proportional to thenumber of capacitors charged. I

DESCRIPTION OF DRAWINGS FIG. 1 is a schematic diagram of the preferredembodiment of the invention wherein a sinusoidal peak voltage is dividedby a factor of two.

FIG. 2 is a schematic diagram of a modification of the embodiment ofFIG. 1 wherein a sinusoidal peak voltage is divided by a factor ofthree.

FIG. 3 is a schematic diagram of a modification of the embodiment ofFIG. 1 wherein a transistor switch is substituted for the SCR switch.

FIG. 4 is a timing diagram for the invention as shown in FIG. 1 whereinvoltage is plotted against time at various nodes in the circuit.

DESCRIPTION OF PREFERRED EMBODIMENT In the preferred embodiment of theinvention (FIG.

1), a sinusoidal voltage source V, typically 115 volts AC, is impressedacross input terminals 11, 13, the terminal 13 being connected to areference potential, such as ground. The terminals 11, 13 are seriallyinterconnected by a pair of resistors 15, 17 and a silicon controlledrectifier 19, the anode of the SCR being poled toward the terminal 13and its connection with resistor 17 being denominated node A. Thegate-terminal connection of SCR 19 is connected between the serialresistors 15, 17 forming node B.

In parallel with the pair of resistors 15, 17, are serially connected aresistor 21 and two diodes 23, 25 with diode 23 being connected toresistor 21 and the interconnection between resistors 15, 21 beingdenominated node C. The diodes 23, 25 are poled with their cathodestoward terminal 11 and the interconnection of these two diodes formsnode D.

Capacitor 27 and dioddes 29, 31 are serially connected across diode 25with capacitor 27 poled with its negative side tied to node D, and thediodes 29, 31 poled with their cathodestoward capacitor 27. Theinterconnection between capacitor 27 and diode 29 is denominated node Eand the interconnection between diodes 29, 31, node F.

From node E to node F, in parallel with diode 29, is a serial connectionof diodes 33, 35 and capacitor 37, with diode 33 connected to node E andcapacitor 37 tied to node F. The diodes 33, 35 are poled with theircathodes toward their interconnection, which is denominated as node G,and capacitor 37 is poled with its positive side toward its connectionto diode 35, this interconnection forming node H.

Diode 39 is interconnected between node H and terminal 13 which is tiedto reference potential and is poled with its cathode toward node H.Interconnected between node G and terminal 13 is output capacitor 41,positioned with its plus side connected to node G.

Terminals 43 and 45 are the output terminals of the circuit withterminal 43 being connected to the plus side of capacitor 41 andterminal 45 being tied to the negative side of capacitor 41.

Silicon controlled rectifier 19 is a PNPN semiconductor device. Withreverse voltage impressed upon the device SCR 19 blacks the flaw ofcurrent up to the breakover point, V At this point, the blockingresistance of SCR 19 decreases almost intantaneously to a very low valueand current flow through the device is then limited only to the externalvoltage and circuit impedance. At anode-to-cathode voltage less than VSCR 19 can be switched into the high conduction state (turned on) by alow level gate-to-cathode current. SCR 19 can be turned off by reducingtheflow of anode current. This is accomplished by reducing the supplyvoltage to zero, as occurs in every cycle of AC circuits, or bydiverting anode current around SCR 19 for the few microseconds requiredfor the device to recover its blacking state.

Resistors l5 and 17 form a voltage divider to limit the gate current 1,to SCR l9. Resistor 17 is chosen small enough to prevent any spuriousspikes from triggering SCR 19. Resistor 21 limits the current throughthe capacitor charging circuit.

The diodes 23, 25, 29, 31, 33, 35 and 39 in the circuit may all be ofthe same value. The capacitors 27, 37 and 41 in the circuit arepreferably of the tantalytic or electrolytic type. The capacitor valuesof the capacitors 27, 37 in the diode branches should be equal fordividing the input voltage by two. The output capacitor 41, across whichthe output voltage is discharged, must be of a value to handle thedischarge of the voltage stored in capacitors 27 and 37. The capacitors27, 37 in the capacitor bank will charge in series to the peak inputvoltage, each capacitor withstanding half this value. The invention inoperation is driven 'by the input voltage. As the sinusoidal input toterminal 11 swings positive (FIG. 4), current flows through resistors 15and 17 to node A which is shunted to ground as SCR 19 turns on. Nocurrent is flowing in the resistor 21 line of the network because of theblocking action of diode 23. This state continues until the inputvoltage swings negative. When the input voltage goes negative, SCR 19turns off and node A floats in the circuit.

With the input at terminal 11 a negative value, and terminal 13 held toground, the biasing of the diode capacitor link of the circuit iscorrect for a flow of current from terminal 13 to terminal 11 via thepath of diode 39, charging capacitor 37, through diode 29, chargingcapacitor 27, through diode 23 and resistor 21. There is a total voltagedrop of V from terminal 113 to terminal 11. At steady state, whichbegins when the input voltage reaches its negative peak and continuesuntil it crosses the zero axis to a positive value, the capacitors willbe charged in series to the peak magnitude of the input voltage, V,,,where V, is V in (RMS) X l/O.707. Capacitors 27 and 37, being of equalvalue, will each have one-half of this voltage impressed across them.

During the period when the input voltage is a negative value, there isno current flow through the discharging diodes 25, 31, 33 or 35.

When the input voltage swings to a positive value, SCR 19 is triggeredinto a conductive state which effectively again shunts node A to ground.When this occurs, there is a current through diodes 25 'and 31 from nodeA to node D and node F, respectively, discharging the negative plates ofcapacitors 27 and 37 concurrently, which of necessity forces a dischargeof the positive plates of capacitors 27 and 37 concurrently. Under thesecircuit conditions, there is a current flow through diodes 33 and 35discharging capacitors 27 and 37 in parallel across capacitor 41 and theoutput terminals 43, 45.

During the positive portion of the input voltage, there is no currentflow through the charging diodes 23, 29, and 39.

The output pulse is a decaying exponential whose three sigma value is afunction of the time constant of the circuit and whose magnitude isapproximately V,,/2.

By adjusting the magnitude of the output capacitor 41, the output can besmoothed to a DC level approaching V,,/2.

It is well to note that SCR 19 does not turn off and turn oninstantaneously as the input voltage crosses the zero axis (FlG. 4).There is a few microseconds delay in each instance. This delay isreflected in the discharging of the bank capacitors 27, 37.

Proper circuit component values are chosen for operating in the voltageand frequency ranges of the environment of the circuit. Values for thecircuit-as shown in the preferred embodiment in a typical circuitenvironment are:

Resistor l5 ohms Resistor 17 25k ohms Resistor 21 680 ohms SCR 19 250v,1 amp Capacitor 27 20uf, lOOv Capacitor 37 20uf, 100v Capacitor 41 40uf,lOOv Diode 23) Diode 25) Diode 29) 1 amp, 500 piv Diode 31) siliconDiode 33) Diode 35) An alternate embodiment of the invention (FIG. 2)differs from the preferred embodiment in that there are threecapacitors, of equal value, instead of two capacitors, in the capacitorbank.

In the alternate embodiment all the components (with like referencenumerals) of the preferred embodiment are utilized with an additionalcapacitor 49 in the bank with its attendant charging diode 53 anddischarging diodes 51, 47. Diode 47, capacitor 49 and diode 51 areconnected in parallel with diode 31, capacitor 37 and diode 35 and aresimilarly poled. The cathode of diode 39 is now connected to theintersection of diode 51 and capacitor 49 and diode 53 interconnectsterminal 13 with the junction of capacitor 49 and diode 47. In thecircuit of the alternate embodiment, there is the serial charging ofcapacitors 27, 37, and 419 so that the divisional factor is 3, and withan input peak magnitude of V, the output magnitude is V,,/3. The outputof this embodiment has the same waveform and period as the output of thepreferred embodiment described herein.

A logical extension of the embodiments described herein is theN-dimensional general configuration wherein the divisional factor is N.In this general configuration there are N capcitors in the capacitorbank. With an input voltage peak magnitude of V,,, the output magnitudeis V,,,-, and this output has the same waveform and period as thepreferred embodiment.

The general N-configuration could be extended to include the capabilityof switching into and out of the capacitor bank, additional capacitorsto change the divisional factor of the circuit as needed. A simpleswitching network could be included to add capacitors and theirassociated diode circuitry to the capacitor bank. In each instance, theoutput waveform and period would remain constant for a given input tothe circuit and the magnitude would vary inversely to the number ofcapacitors in the bank.

A second alternate embodiment of the invention (FIG. 3) differs from thepreferred embodiment in that a transistor 55 with its associatedcollector diode 57 is substituted for the SCR 19. Under some loadconditions difficulty may be experienced in turning off the SCR 19. Thesubstitution of the equivalent transistor circuit and readjustment ofR15 and R17 eliminates the SCR turn off problem. In this configurationwherein the substitution of a transistor is made, the circuit waveformsare essentially identical to the configuration with the SCR, except, thepulses have slower rise and fall times and therefore less noise isgenerated in the circuit.

What is claimed is: l

l. A voltage reducing rectifier circuit for an altemating voltage sourcewith respect to a reference potential comprising:

a plurality of capacitors;

a plurality of passive unidirectional means for connecting saidcapacitors in series between said reference potential and saidalternating voltage source, each of said plurality of capacitors beingconnected between successive ones of said passive unidirectional meansfor charging said plurality of capacitors during a half-cycle of saidalternating voltage source; 1

a plurality of pairs of passive unidirectional means connected inparallel as an output circuit, each of said plurality of capacitorsbeing also respectively connected between individual ones of said pairsof passive unidirectional means; and

a single gate-controlled, gating means sensitive to the phase andmagnitude of said alternating voltage source and connected to saidoutput circuit, for completing a circuit for permitting dischargecurrent to flow between said reference potential and said output circuitonly during the other half-cycle of said voltage source.

2. The circuit of claim 1 wherein each of said unidirectional meansincludes a diode and wherein said plurality of capacitors are of equalvalue.

3. The circuit of claim 1 further including an output capacitorconnected in parallel with said output circuit and said single gatingmeans.

4. The circuit of claim 1 wherein said gating means includes controlledrectifier gating means.

5. The circuit of claim 4 including a voltage divider connected betweensaid voltage source and said controlled rectifier gating means, saidcontrolled rectifier gating means including a silicon controlledrectifier and end of said divider and to said output circuit, a baseconnected to a mid-point of said divider, and a collectorunidirectionally connected to said reference potential..

1. A voltage reducing rectifier circuit for an alternating voltagesource with respect to a reference potential comprising: a plurality ofcapacitors; a plurality of passive unidirectional means for connectingsaid capacitors in series between said reference potential and saidalternating voltage source, each of said plurality of capacitors beingconnected between successive ones of said passive unidirectional meansfor charging said plurality of capacitors during a half-cycle of saidalternating voltage source; a plurality of pairs of passiveunidirectional means connected in parallel as an output circuit, each ofsaid plurality of capacitors being also respectively connected betweenindividual ones of said pairs of passive unidirectional means; and asingle gate-controlled, gating means sensitive to the phase andmagnitude of said alternating voltage source and connected to saidoutput circuit, for completing a circuit for permitting dischargecurrent to flow between said reference potential and said output circuitonly during the other half-cycle of said voltage source.
 2. The circuitof claim 1 wherein each of said unidirectional means includes a diodeand wherein said plurality of capacitors are of equal value.
 3. Thecircuit of claim 1 further including an output capacitor connected inparallel with said output circuit and said single gating means.
 4. Thecircuit of claim 1 wherein said gating means includes controlledrectifier gating means.
 5. The circuit of claim 4 including a voltagedivider connected between said voltage source and said controlledrectifier gating means, said controlled rectifier gating means includinga silicon controlled rectifier and said rectifier having its gate tiedto an intermediate point of said voltage divider.
 6. The circuit ofclaim 1 wherein said gating means includes transistor gating means. 7.The circuit of claim 6 wherein said transistor gating means includes atransistor and the rectifier circuit also includes a resistive voltagedivider connected between said voltage source and said transistor andwherein said transistor has an emitter connected to an end of saiddivider and to said output circuit, a base connected to a mid-point ofsaid divider, and a collector unidirectionally connected to saidreference potential.